Cache Coherence
The minimal requirement that writes to a single address are seen in the same order by all processors. Implied by virtually all hardware models, and identical to Goodman's cache consistency in the Steinke–Nutt lattice. Much weaker than SC; incomparable to PRAM and causal consistency; strictly weaker than processor consistency and strictly stronger than slow consistency.
Properties
Property vector author-extrapolated — set only where the model’s definition pins the cell down (unknown cells are omitted); cells citing a specific source are marked.
- Reordering sound
- yes Store→Load
- yes Store→Store
- yes Load→Load
- yes Load→Store
- Reasoning guarantees
- yes Coherence
- yes No undefined behaviour
- no In-order execution
- no No out-of-thin-air
Ordering relationships
- Strictly weaker than
- Relaxed Memory Order (RMO) — RMO still enforces per-address coherence; weaker models could violate it.
- ARM Memory Model — ARM enforces coherence (per-address total order) as a baseline.
- IBM POWER Memory Model — POWER enforces coherence as a baseline.
- DEC Alpha Memory Model — Alpha guarantees per-location (SC-per-location) coherence and enforces cross-location ordering only via mb/wmb fences (Alpha Architecture Reference Manual; Alglave, Maranget & Tautschnig, Herding Cats, TOPLAS 2014, p.4); bare coherence has neither. Separating outcome: MP+mb+mb, forbidden by Alpha, allowed by Coherence. Cited (Alpha has no herd7 cat model), not machine-run.
- Intel Itanium (IA-64) Memory Ordering — Itanium guarantees cache coherence (a per-location total order on writes; Intel Itanium SDM, memory-ordering rules) and adds cross-location ordering via ld.acq/st.rel/mf; bare coherence has neither. Separating outcome: MP with acquire/release or mf on both sides, forbidden by Itanium, allowed by Coherence. Cited (no herd7 cat model for IA-64), not machine-run.
- Processor Consistency (PC) — Processor consistency is strictly stronger than cache consistency (Goodman 1989; Steinke & Nutt 2004). The Coherence node is Goodman's cache consistency.
- Strictly stronger than
- Slow Consistency — Slow consistency is strictly weaker than cache consistency (Hutto & Ahamad 1990; Steinke & Nutt 2004).
- Incomparable with
- PRAM (Pipelined RAM) Consistency — PRAM and cache consistency are incomparable: PRAM orders a process's own writes globally but not per-location, cache consistency the converse (Goodman 1989; Steinke & Nutt 2004).
- Causal Consistency — Causal and cache consistency are incomparable (Steinke & Nutt 2004).
References
- Sarita V. Adve, Mark D. Hill. Weak Ordering — A New Definition. ISCA 1990, 1990. doi:10.1145/325164.325100
- James R. Goodman. Cache Consistency and Sequential Consistency. Technical Report 61, IEEE Scalable Coherent Interface Working Group / University of Wisconsin-Madison, 1989.
- Robert C. Steinke, Gary J. Nutt. A Unified Theory of Shared Memory Consistency. Journal of the ACM 51(5), 2004. arxiv.org/abs/cs/0208027
- Sarita V. Adve, Kourosh Gharachorloo. Shared Memory Consistency Models: A Tutorial. IEEE Computer 29(12), 1996. doi:10.1109/2.546611