Cache Coherence
The minimal requirement that writes to a single address are seen in the same order by all processors. Implied by virtually all hardware models. Stronger than nothing, but much weaker than SC.
Ordering relationships
- Strictly weaker than
- Relaxed Memory Order (RMO) — RMO still enforces per-address coherence; weaker models could violate it.
- ARM Memory Model — ARM enforces coherence (per-address total order) as a baseline.
- IBM POWER Memory Model — POWER enforces coherence as a baseline.
References
- Sarita V. Adve, Mark D. Hill. Weak Ordering — A New Definition. ISCA 1990, 1990. doi:10.1145/325164.325100