Intel Itanium (IA-64) Memory Ordering
The memory-ordering model of the Intel Itanium (IA-64) architecture. Ordinary loads and stores are 'unordered' and may be reordered in all four directions; ordering is imposed explicitly by acquire loads (ld.acq), release stores (st.rel) and the memory fence (mf) — a ld.acq is ordered before every following memory operation and a st.rel after every preceding one. This ISA-level acquire/release design is closer in spirit to ARMv8's LDAR/STLR than to a bare relaxed-plus-barrier model like POWER/ARMv7. Cache coherence (a per-location total order on writes) is guaranteed. Two independent academic formalizations exist: Yang et al. (CHARME 2003), a logic-programming/SAT axiomatization of the ordering rules, and Higham, Jackson & Kawash (2007), a programmer-centric 'views' characterization which finds the vendor specification not fully tight (the model lies between two closely related definitions). Neither formalization nor the vendor manual states a machine-checked containment or incomparability against another model in this dataset, so no strength edge is drawn.
Properties
Property vector author-extrapolated — set only where the model’s definition pins the cell down (unknown cells are omitted); cells citing a specific source are marked.
- Reordering sound
- yes Store→Load
- yes Store→Store
- yes Load→Load
- yes Load→Store
- Reasoning guarantees
- yes Coherence
- yes No undefined behaviour
- no In-order execution
- yes No out-of-thin-air
Ordering relationships
- Strictly stronger than
- Cache Coherence — Itanium guarantees cache coherence (a per-location total order on writes; Intel Itanium SDM, memory-ordering rules) and adds cross-location ordering via ld.acq/st.rel/mf; bare coherence has neither. Separating outcome: MP with acquire/release or mf on both sides, forbidden by Itanium, allowed by Coherence. Cited (no herd7 cat model for IA-64), not machine-run.
References
- Intel Corporation, Hewlett-Packard. Intel Itanium Architecture Software Developer's Manual, Volume 2: System Architecture (memory-ordering rules). Intel Corporation, 2002. www.intel.com/content/www/us/en/products/docs/processors/itanium/itanium-architecture-software-developer-rev-2-3-manual.html
- Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, Konrad Slind. Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT. CHARME 2003, LNCS 2860, 2003. doi:10.1007/978-3-540-39724-3_9
- Lisa Higham, LillAnne Jackson, Jalal Kawash. What is Itanium Memory Consistency from the Programmer's Point of View?. ENTCS 174(9) (TV@FLoC 2006), 2007. doi:10.1016/j.entcs.2007.04.007