NVIDIA Tile IR Memory Model
The memory model of NVIDIA's Tile IR, a tile-based virtual ISA introduced with CUDA 13.1 (2026) as a lower-level compilation target for tile programs (e.g. the experimental Triton-to-Tile-IR backend). This axiomatic, scoped model defines coherence order, happens-before, program order, 'morally strong' accesses, reads-from and token-based dependency ordering, with scopes tile_block/device/sys; global memory accesses are unordered by default. NVIDIA's documentation states the axioms and relations are intended to be a strict weakening of the PTX model. Vendor documentation only — no peer-reviewed formalisation or proof.
Properties
Property vector author-extrapolated — set only where the model’s definition pins the cell down (unknown cells are omitted); cells citing a specific source are marked.
- Reordering sound
- yes Store→Load
- yes Store→Store
- yes Load→Load
- yes Load→Store
- Reasoning guarantees
- yes Coherence
- no In-order execution
- yes No out-of-thin-air
- Atomicity guarantees
- no Multicopy atomic
Ordering relationships
- Strictly weaker than
- NVIDIA PTX Memory Model — NVIDIA Tile IR docs §7: 'The axioms and relations of the Tile IR memory model are intended to be a strict weakening of the PTX memory model.' Vendor-asserted (note the hedged 'intended to be' language); not independently proven or machine-checked.
References
- NVIDIA. Tile IR Memory Model (CUDA Tile IR documentation, §7). NVIDIA CUDA Toolkit Documentation (CUDA 13.1), 2026. docs.nvidia.com/cuda/tile-ir/latest/sections/memory_model.html