ARMv8 / AArch64 Memory Model
A strengthened, formally specified model for ARMv8. Multi-copy atomic (stores become visible to all threads simultaneously). Introduces the LDAR/STLR acquire-release instructions. Strictly stronger than ARMv7.
Ordering relationships
- Strictly weaker than
- Total Store Order (TSO) — ARMv8 allows more reorderings than TSO though it is multi-copy-atomic. The TSO ⊆ ARMv8 containment is a model-level monotonicity argument over different instruction sets, not a cited theorem, so the edge is recorded as litmus-grade (provisional): the one-sided witness does not by itself exclude incomparability.
- Strictly stronger than
- ARM Memory Model — ARMv7 is non-MCA and weaker than ARMv8.
- Compilation target of
- Intermediate Memory Model (IMM) — IMM compiles correctly to ARMv8.
- Linux Kernel Memory Model (LKMM) — Linux kernel primitives compile correctly to ARMv8/AArch64.
- Incomparable with
- RISC-V Weak Memory Ordering (RVWMO) — Both are multi-copy atomic and coincide on every standard litmus family over the common instruction set (verified against herd7's aarch64.cat and riscv.cat). The incomparability is instruction-level: RISC-V's fence.tso (which allows SB) and the RCsc/RCpc atomics differ from ARMv8's. See litmus/incomparable/ARMv8-vs-RVWMO.
References
- Christopher Pulte, Shaked Flur, Will Deacon, Jon French, Susmit Sarkar, Peter Sewell. Simplifying ARM Concurrency: Multicopy-atomic Axiomatic and Operational Models for ARMv8. POPL 2018, 2018. doi:10.1145/3158107