RISC-V Weak Memory Ordering RVWMO
The official memory model for RISC-V. A carefully designed relaxed model weaker than TSO but stronger than POWER/ARM. Defines ordering via FENCE instructions and load-reserved/store-conditional pairs. Formally specified in the RISC-V ISA manual.
Ordering relationships
- Strictly weaker than
- Total Store Order (TSO) — RVWMO is weaker than TSO: it allows store-store and load-load reorderings TSO forbids. The containment rests on the same model-level monotonicity argument as TSO → ARMv8 (RISC-V's Ztso extension makes RVWMO+TSO near-definitional), recorded as litmus-grade for consistency under the stricter standard.
- Compilation target of
- Linux Kernel Memory Model (LKMM) — Linux kernel primitives compile correctly to RISC-V (RVWMO).
- Incomparable with
- ARMv8 / AArch64 Memory Model — Both are multi-copy atomic and coincide on every standard litmus family over the common instruction set (verified against herd7's aarch64.cat and riscv.cat). The incomparability is instruction-level: RISC-V's fence.tso (which allows SB) and the RCsc/RCpc atomics differ from ARMv8's. See litmus/incomparable/ARMv8-vs-RVWMO.
References
- Andrew Waterman, Yunsup Lee, Krste Asanovic, David Patterson. The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA — Chapter on Memory Model (RVWMO). RISC-V Foundation, 2019.
- Christopher Pulte, Jean Pichon-Pharabod, Jeehoon Kang, Sung-Hwan Lee, Chung-Kil Hur. Promising-ARM/RISC-V: A Simpler and Faster Operational Concurrency Model. PLDI 2019, 2019. doi:10.1145/3314221.3314609