Relaxed Memory Model Zoo

Ordering relationships

Strictly weaker than

• Sequential Consistency (SC) — TSO allows store-load reordering; SC does not.

Strictly stronger than

• Partial Store Order (PSO) — PSO additionally allows store-store reordering to different addresses.
• ARMv8 / AArch64 Memory Model — ARMv8 allows more reorderings than TSO though it is multi-copy-atomic. The TSO ⊆ ARMv8 containment is a model-level monotonicity argument over different instruction sets, not a cited theorem, so the edge is recorded as litmus-grade: the strict order is argued (monotonicity) and corroborated by the sweep, not independently proven — a genuine strict order, drawn lighter than a literature-backed one, not an edge that might be incomparable.
• RISC-V Weak Memory Ordering (RVWMO) — RVWMO is weaker than TSO: it allows store-store and load-load reorderings TSO forbids. The containment rests on the same model-level monotonicity argument as TSO → ARMv8 (RISC-V's Ztso extension makes RVWMO+TSO near-definitional), recorded as litmus-grade for consistency under the stricter standard.
• Relaxed Memory Models: an Operational Approach (RMMOA) — Like PSO, RMMOA's hierarchical store buffers additionally permit store→store reordering to distinct addresses, which TSO forbids.

Equivalent to

• x86-TSO — x86-TSO formalises TSO for x86; behaviourally equivalent for standard operations.
• Buffered Memory Model (BMM) — BMM is a pragmatic TSO-style buffered model proposed as a candidate Java memory model; on the store-buffer relaxations it coincides with TSO.

Compilation target of

• WebAssembly Memory Model (Wasm) — Watt et al. 2019 Fig. 19 tabulates the compilation of Wasm memory accesses to x86 (whose ISA model is TSO), following the established C/C++11 SC-atomic schemes [Sewell & Sevcik 2016]; full mixed-size correctness is flagged as an open problem (§7.1.1).